|
Feature
|
2014
|
Roadmap
|
|
|
Standard
|
Advanced
|
|
|
Layer count
|
1 – 28L
|
36L
|
60L
|
|
Minimum dielectric thickness
|
0.075mm for PCB
0.025mm for FPC
|
≤0.05mm for PCB
0.015mm for FPC
|
≤0.05mm for PCB
0.012mm for FPC
|
|
HDI / Buried – blind via
|
Y
|
Y
|
Y
|
|
Copper filled BVH (Y/N)
|
Y
|
Y
|
Y
|
|
Capped via (Y/N)
|
Y
|
Y
|
Y
|
|
Maximum board size (mm)
|
1000 x 580
|
1200 X 610
|
1200 X 610
|
|
Minimum board thickness
2L
|
0.2 mm for rigid
0.05mm for 1L FPC
0.12mm for 2L FPC
|
0.15mm for rigid
0.05mm for 1L FPC
0.12mm for 2L FPC
|
≤0.1mm for rigid
0.05mm for 1L FPC
0.12mm for 2L FPC
|
|
Minimum board thickness
>=4L (mm)
|
0.40mm for PCB
0.20 for FPC
|
0.35mm for PCB
0.16 for FPC
|
≤0.30mm for PCB
0.16 for FPC
|
|
Maximum PCB thickness
|
7.0
|
10.0
|
10.0
|
|
Minimum track / gap IL of 0.5 Oz
|
0.075mm
|
0.05mm
|
0.05mm
|
|
Minimum track / gap OL of 0.5 Oz
|
0.075mm
|
0.05mm
|
0.05mm
|
|
Surface finish
|
ENIG / GF / OSP / I Ag / HASL (lead) / HASL (Leadfree) / Soft gold
|
ENIG / GF / OSP / I Ag / HASL (lead) / HASL (Leadfree) / Soft gold
|
ENIG / GF / OSP / I Ag / HASL (lead) / HASL (Leadfree) / Soft gold
|
|
Layer to layer registration
|
0.10mm
|
≤ 0.075mm
|
≤ 0.075mm
|
|
Minimum hole (mech) (mm/mil)
|
0.20mm
|
0.15mm
|
0.15mm
|
|
Minimum hole (laser) (mm/mil)
|
0.10mm
|
0.06mm
|
0.075mm
|
|
Aspect ratio PTH
|
10:1
|
13:1
|
15:1
|
|
Aspect ratio BVH
|
0.8:1
|
1.3:1
|
1.3:1
|
|
Finish hole tolerance (PTH)
|
± 0.10mm
|
± 0.05mm
|
± 0.05mm
|
|
Finish hole tolerance (NPTH)
|
± 0.05mm
|
≤ ± 0.05mm
|
≤ ± 0.05mm
|
|
Maximum Cu weight OL
|
3
|
5oz
|
10oz
|
|
Controlled impedance (+/- X%)
|
Others ± 10%
|
± 5%
|
± 5%
|
|
|
|
|
|
|
Rigid-flex (Y/N)
|
Y
|
Y
|
Y
|
|
Flexible (Y/N)
|
Y
|
Y
|
Y
|
|
Embedded components (Y/N)
|
Y
|
Y
|
Y
|
